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Verification Engineer I
Date Posted: 04/25/2024
Job #: 3062507
Location: Centennial
Company Description
Join SEAKR Engineering, a leading-edge provider of advanced electronics for
space applications. Pushing the boundaries of technology on a mission to
change the world for the better from space.
Job Description
SEAKR is seeking a Verification Engineer who is responsible for developing
verification and simulation strategies, creating a digital test plan and
providing coverage metrics.
The Engineer is responsible for the construction and maintenance of simulation
environments using System Verilog with UVM (Universal Verification
Methodology), and performing and evaluating regression tests for a design
under test.
The candidate must be able to extract and derive test requirements and
sequences for an interface or interfaces based on available design
documentation and requirements.
Ability to architect and construct full test environments for simple devices
using UVM, including coverage, is a plus.
Ability to analyze and write System Verilog is required.
The candidate shall be capable of diagnosing sophisticated test failures and
filing results and be capable of analyzing code coverage to adjust agent
sequence behavior.
Ability to analyze Verilog RTL to diagnose test failures is required.
Ability to diagnose VHDL RTL is a plus.
...
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