CPU Silicon Timing Correlation Engineer
Boston, Massachusetts, United States
Hardware
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In this highly visible role, you will be at the center of a chip design effort interfacing with many disciplines, with a critical impact on getting functional products to millions of customers quickly. You will be a member of a silicon timing characterization team. In this highly cross disciplinary role you will execute tasks that contribute to debugging physical issues in silicon and correlating silicon timing behavior with pre-silicon models.
Key Qualifications
- Minimum BS and 10+ years of relevant industry experience
- Good all round hardware and data analysis skills
- Good understanding of VLSI design practice and static timing analysis
- Data analysis skills and experience using Python/JMP
- Understanding of SoC/CPU architecture is desirable
- Grasp of structural test (ATPG, MBIST) methods is highly desirable
- Proven ability to lead a broad team towards successful closure on timing debug issues
- Track record of innovation in the area of silicon timing correlation
- Lab experience (system, board or tester platform) required
- Excellent teamwork and communication. Ability to work with multiple teams in delivering a solution.
Description
- Create and refine methodologies for isolating and debugging timing failures in system and on tester
- Develop, modify and deploy tests on silicon as part of characterization plan
- Analyze silicon parametric data and correlate with empirical observations
- Maintain and improve infrastructure for gathering silicon parametric data at scale
- Work with partner teams e.g. DFT, physical implementation, logic design to debug issues and improve methodology
- Enhance existing silicon debug features and conceive of new ones.
Education & Experience
Minimum BS and 10+ years of relevant industry experience