CPU Cache Microarchitect/RTL Engineer
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Apple’s Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products, including the iPhone, iPad, Watch, Vision Pro, and Mac. We are looking for an experienced technical leader to drive CPU multi-level cache subsystem architecture and RTL development for multi-processor systems.
As a CPU Cache Microarchitect/RTL Engineer, you will own or participate in the following:
• Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification.
• RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals.
• Verification - support the verification team in test bench development, formal methods, and simulation/emulation for formal verification
• Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance.
• Design delivery - work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power.
- Minimum BS and 10+ years of relevant industry experience
- Knowledge of microprocessor architecture
- Knowledge of Verilog and/or VHDL
- Experience with simulators and waveform debugging tools
- Knowledge of logic design principles along with timing and power implications
- Expertise in one or more of the following areas:
- Coherence protocols and interconnects
- High performance (low latency, high bandwidth) design techniques
- Memory subsystem queuing, scheduling; starvation and deadlock avoidance
- SRAM design basics
- Multiple clock/power domains and power management strategies
- Prefetchers, replacement policies
- Debug capabilities
- DFT strategies
- Error detection and correction
- Understanding of low power microarchitecture techniques
- Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
- Experience in C or C++ programming
- Experience using an interpretive language such as Perl or Python
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