NAND Packaging Engineer
Santa Clara Valley (Cupertino), California, United States
Hardware
Do you like to work on groundbreaking technologies that enable amazing new products? Do you have the attention for details and love for excellence to work towards an extraordinary result? Envision what you could do here!
At Apple, we believe new insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish! Apple's SEG Packaging team invents, designs, develops and integrates electronic packaging solutions for the Apple’s internal and customized external components of hardware for its consumer electronic products.
We are looking for a hard-working NAND Packaging Engineer to join our team. In this highly visible role, you will own and drive the memory package development in support of Apple's external memory vendors and steering their packaging design compatibility to Apple's system components.
Description
As a NAND Packaging Engineer, your main focus will be on defining memory package architecture, die pad layout, package form factor, interconnect and package density, and will support the system and product teams and overall program through the development and NPI cycle.
- Define the memory package POR (plan of record): Package architecture, technology, process, form factor, layout, bill of materials (BOM), design rules, thermo-mechanical, signal integrity, power integrity.
- Publish internal package specs for customized memory Establish trusting and collaborative relationships and communication channels, directly collaborating with vendors for memory package development and qualification.
- Review, drive, and approve memory vendor DOEs, characterization plans, technology qualification.
- Drive industry with sophisticated package design rules, processes, materials, and groundbreaking specifications.
- About 10% international travel required.
Minimum Qualifications
Key Qualifications
- Experience in the packaging design and assembly process development for stacked-die memory packages.
- Proven knowledge of wirebond and flip-chip assembly process applied to thin-die stacking.
- Hands on experience using packaging materials, substrate technology, and their mechanical and thermal behaviors.
- Proficient in assembly design rules, SIPI, and layout tradeoffs to enable high performance DDR or differential signaling.
- Confirmed abilities working in package test and reliability, system-level downstream process interaction, and packaging inspection metrology.
- Excellent logic, critical thinking skills with strong engineering physics and data driven analysis.
- Strong written and verbal communication skills for working with internal multi-functional teams and OSATs.
Preferred Qualifications
Education & Experience
- BS and 10+ years of relevant industry experience.
Additional Requirements
Pay & Benefits
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.